Programmable Architecture Performance Using Common Sub-graph Extraction and New Packing Method in Compute Intensive Media, Scientific and Bio-chemical Applications

Increasing demand for configuration time aware processing with stringent constraints for flexibility necessitates the design and development of a dynamically fast reconfigurable processor. This paper focuses on the extraction of tasks or core clusters in Control Data Flow Graphs (CDFGs) of applications, architectures to embed them in Hybrid-FPGA environments and the routing architecture necessary to support the structure. Each pure sequential code inside the control flow structure is called a basic block in compiler terminology. Tasks or core clusters are basically recurring computation patterns implemented as ASICs on non-reconfigurable area. Those are obtained through the common sub-graph analysis between basic blocks within and across routines in a given class of application. After removing the common sub-graphs from the CDFG, remaining parts of each basic block are then implemented on LUT based reconfigurable area. Packing mechanism for configurable logic uses live-in live-out variable analysis and scheduling information of CDFGs in it’s cost function in addition to routability and timing driven cost metrics defined by other researchers. Application domains were chosen based on their need for large amounts of parallel operations and correlation between computation patterns. Several complex routines from classes of Multimedia, Mathematical and BioChemical algorithms have been chosen. We have conducted experiments on MPEG-4 VVM [1], Gnu Scientific Library (GSL)[2], Biochemical Algorithms Library (BALL)[3] and NAMD molecular modeling library[4]. A map report based on Spartan 2E architecture was obtained based on the synthesis report. Results show that partial reconfiguration with the use of computation cores embedded in a sea of LUTs offer the potential for massive savings in gate density and by eliminating the need for unnecessary and redundant subcircuit pattern configurations.